1. Field of Application
The present invention relates to an analog switch and to a switched-capacitor filter which incorporates the analog switch.
2. Description of Related Art
Since the characteristic response time of a semiconductor pressure sensor is several milliseconds, such a sensor also detects noise, i.e., high-frequency ripple components. Detection of these high-frequency components will result in a lowering of the detection resolution of the sensor, rendering it unsuitable for applications in which high accuracy is necessary. For that reason, there is a requirement for a circuit which will enable high accuracy to be maintained for such a sensor, even when high-frequency ripple components are detected.
One method of removing of high-frequency components from the output of a semiconductor pressure sensor (referred to in the following simply as a pressure sensor) is to transfer the output signal from the sensor through a low-pass filter circuit having a suitably low cut-off frequency. A specific example is shown in FIG. 8, in which a switched-capacitor filter circuit 200 functions as a low-pass filter that operates on the output detection signal from a pressure sensor, supplied via a differential amplifier 100. This enables the detection frequency range of the pressure sensor to be set appropriately, by selecting a suitably low cut-off frequency for the switched-capacitor filter.
In FIG. 8, the pressure sensor is formed of a set of four piezo-resistive elements R1, R2, R3, R4, each being a semiconductor device with a diffused-impurity layer structure, which are formed on a diaphragm. The piezo-resistive elements R1 to R4 are connected in a bridge circuit as shown, with a current from a current source being passed through two opposing terminals of the bridge circuit and with a voltage which appears between the remaining pair of opposing terminals of the bridge circuit being inputted to the differential amplifier 100. The differential amplifier 100 thereby outputs a pressure detection signal that is inputted to the switched-capacitor filter circuit 200. The switched-capacitor filter circuit 200 is formed of a switched-capacitor filter 103, a frequency-divider circuit 104 and an oscillator circuit 105. The oscillator circuit 105 generates a reference clock signal (shown in the timing diagram of FIG. 10) that is supplied to the frequency-divider circuit 104, which thereby generates a synchronized pair of clock signals respectively designated as the first-phase clock pulse signal φ1 and the second-phase clock pulse signal φ2, as well as their respective inverse signals φ1 bar and φ2 bar. The relationship between the first-phase clock pulse signal φ1 and second-phase clock pulse signal φ2 and the reference clock signal are shown in FIG. 10.
FIG. 9 shows an example of the circuit of a prior art switched-capacitor filter 103, which incorporates analog switches whose operation timings are controlled by the first-phase clock pulse signal φ1 and second-phase clock pulse signal φ2 of FIG. 10. As shown, the switched-capacitor filter 103 is formed of an operational amplifier OP1, first, second and third capacitors C1, C2, C3, and first to sixth analog switchcs SW1 to SW6, with the capacitor C3 being connected between the output terminal and inverting input terminal of the operational amplifier OP1, and with the non-inverting input terminal of the operational amplifier OP1 receiving a reference voltage Vref. Hence, the operational amplifier OP1 and capacitor C3 are connected as an inverting integrator circuit, with Vref being the common reference level of the input and output signals Vi, Vo of the filter.
Each of the analog switches SW1 to SW6 is made up of an N-channel MOS FET (metal-oxide semiconductor field effect transistor) and a P-channel MOS FET which are connected in parallel. Each of the first to third analog switches SW1 to SW3 is set in the on (i.e., conducting) state only during each interval in which the first-phase clock pulse signal φ1 is at the H level (i.e., high logic level potential) while each of the fourth to sixth analog switches SW4 to SW6 is set in the on state only during each interval in which the second-phase clock pulse signal φ2 is at the H level.
Referring to FIG. 10, four different conditions of the switched capacitor filter circuit 103 of FIG. 9 can be defined as follows:
(a) the condition during each interval in which the clock pulse signal φ1 is at the H level and the clock pulse signal φ2 is at the L level, designated as the first condition S1;
(b) the condition during each interval which immediately follows a first condition S1 interval and in which both of the clock pulse signals φ1, φ2 are at the L level, designated as the second condition S2;
(c) the condition during each interval in which the clock pulse signal φ1 is at the L level and the clock pulse signal φ2 is at the H level, designated as the third condition S3; and
(d) the condition during each interval which immediately follows a third condition S3 interval and in which both of the clock pulse signals φ1, φ2 are at the L level, designated as the fourth condition S4.
These conditions will be described with respect to the analog switches SW1 to SW6 of the switched-capacitor filter, referring to the circuit operating diagrams of FIG. 11. As shown, in the first condition S1 each of the analog switches SW1, SW2, SW3 is in the on state, while each of the analog switches SW4, SW5, SW6 is in the off state. In the second condition S2, each of the analog switches SW1 to SW6 is in the off state. In the third condition S3, each of the analog switches SW4, SW5, SW6 is in the on state, while each of the analog switches SW1, SW2, SW3 is in the off state. In the fourth condition S4, each of the analog switches SW1 to SW6 is in the off state.
The cut-off frequency fc of such a filter is proportional to the frequency fs of the clock pulse signals φ1, φ2 multiplied by the ratio of values of the capacitors C2, C3. With a usual type of pressure sensor apparatus, it is necessary to use a cut-off frequency in the range of approximately 100 Hz to 400 Hz. If for example a cut-off frequency of 100 Hz is to be used, this can be achieved by setting the values of 0.25 pf for C2, 60 pf for C3, and 150 kHz for the clock pulse frequency fs. It is readily practicable to implement a circuit having such component values as an integrated circuit. However if the cut-off frequency fc is to be made as low as approximately 1 Hz, then assuming that the same values as above are used for fs and for C2, the value of the capacitor C3 would require to be 6000 pf. It is not practicable to form a capacitor having such a large value within an integrated circuit. Hence, if the cut-off frequency fc is to be made as low as 1 Hz, with all elements of the filter being formed within an integrated circuit, it is necessary to lower the clock pulse frequency fs by a factor of 100:1, to approximately 1.5 kHz.
In FIG. 10, the relationship between the first-phase clock pulse signal φ1 and the second-phase clock pulse signal φ2 is such that the interval τ (the duration of the second condition S2) is made extremely short, being approximately 1 μs. This is achieved by using a non-overlap circuit (not shown in the drawings) which operates on the clock pulse signals φ1 and φ2 to provide a delay of approximately 1 μs between each falling edge of the clock pulse signal φ1 and a subsequent rising edge of the clock pulse signal φ2. As a result, the transition from the first condition S1 to the third condition S3 is made as short as possible, so that each sampling charge (on the capacitor C1) is rapidly transferred to the capacitor C3. In that way, the operation during the transition from the second condition S2 to the third condition S3 will be substantially unaffected by a flow of leakage current that may occur in the analog switches during high-temperature operation, even if the sampling frequency (i.e., clock pulse frequency) fs is low.
However with such clock timing, the duration of each interval of the fourth condition S4 will be long, so that as can be understood from FIG. 11, problems arise due to leakage currents that flow in the transistors of the analog switch SW5. That is to say, in general during the fourth condition S4, some leakage current (indicated as IL for condition S4 in FIG. 11) will flow out of or into the analog switch S5, as a charging current or discharge current of the capacitor C3, resulting in a corresponding change in the level of output signal Vo of the filter. This may have a significant effect, when the external flow of leakage current from switch SW5 results from high-temperature leakage currents that flow in the transistors of that switch. The effect increases as the amplitude of variation of the input signal Vi of the filter is reduced. As a result, when there is a high level of external leakage current from the output terminal of switch SW5 (the switch terminal that is connected to the capacitor C3) during each interval of the fourth condition S4, accurate operation cannot be achieved for low values of input signal to the filter, in particular during high-temperature operation of the filter.
FIG. 13 conceptually illustrates leakage current flow paths in the analog switch SW5 of the prior art circuit of FIG. 9 during the fourth condition S4.
FIG. 12 is a cross-sectional view of an example of a configuration for the analog switch SW5 that is typical of the prior art. In that example, the P-channel MOS FET 50 of the switch is formed within an N-well that is formed in an N-type silicon substrate, while the N-channel MOS FET 51 is within a P-well that is formed in the N-type silicon substrate, with a PN junction being formed between the P-well and the N-type substrate. A fixed reverse bias voltage equal to the supply voltage Vcc is applied across this PN junction, so that respective leakage current flow through the source and drain regions, via this PN junction.
Referring to FIGS. 12 and 13, in the case of the N-channel MOS FET 51, leakage currents I50 and I51 flow from the source and drain electrodes through the P-well to the substrate potential-setting terminal 81, which is fixed at ground potential. In the case of the P-channel MOS FET 50, leakage currents I60 and I61 flow from a potential-setting terminal 80, which is fixed at Vcc, through the N-well to the source and drain electrodes.
In general, the magnitude of the leakage current I51 will not be equal to that of the current I61, so that the difference (I51−I61), or the difference (I61−I51) between these, will appear as an external flow of leakage current, i.e., the leakage current IL shown in FIG. 11 which flows into or out of the capacitor C3 of the inverting integrator circuit during the fourth condition S4.
Hence in the prior art it has been difficult to utilize such a switched-capacitor filter, having a sufficiently low value of cut-off frequency for effectively operating on the output signal from a semiconductor pressure sensor to achieve accurate pressure sensing over a wide range of pressure values, with that difficult resulting from a high-temperature leakage current that flows to or from an analog switch of the filter during each interval of operation in the fourth condition S4 described above, with that leakage current flowing as a charging or discharge current of an integrator capacitor (C3) of the filter, during each of the long-duration intervals of condition S4.